A MTJ is a key component in MRAM, spin-torque MRAM, and other spintronic devices and comprises a tunnel barrier layer such as a metal oxide formed between two magnetic layers that together generate a tunneling magnetoresistance (TMR) effect. One of the magnetic layers is a free layer and serves as a sensing layer by switching the direction of its magnetic moment in response to external fields (media field) while the second magnetic layer has a magnetic moment that is fixed and functions as a reference layer. The electrical resistance through the tunnel barrier layer (insulator layer) varies with the relative orientation of the free layer moment compared with the reference layer moment and thereby provides an electrical signal that is representative of a magnetic state in the free layer. In a MRAM, the MTJ is formed between a top conductor and bottom conductor. When a current is passed through the MTJ, a lower resistance is detected when the magnetization directions of the free and reference layers are in a parallel state (“0” memory state) and a higher resistance is noted when they are in an anti-parallel state or “1” memory state. The tunnel barrier is typically about 10 Angstroms thick so that a current through the tunnel barrier can be established by a quantum mechanical tunneling of conduction electrons.
Both of the reference layer and free layer may have a synthetic anti-ferromagnetic (SyAF) configuration in which an outer layer is anti-ferromagnetically coupled through a non-magnetic coupling layer to an inner layer that contacts the tunnel barrier. MgO is often preferred as the tunnel barrier and provides a high TMR ratio when adjoining a CoFe or Fe inner magnetic layer. The TMR ratio is known as dR/R where R is the minimum resistance of the MTJ, and dR is the change in resistance observed by changing the magnetic state of the free layer. A higher TMR ratio improves the readout speed. Moreover, a high performance MTJ requires a low areal resistance RA (area×resistance) value of about 1 ohm-um2, a free layer with low magnetostriction (λ) between −5×10−6 and 5×10−6, low coercivity (Hc), and low interlayer coupling (Hin) between the free layer and reference layer through the tunnel barrier layer.
A high TMR ratio is obtained when the MTJ stack forms a face centered cubic (fcc) crystal structure. However, naturally deposited CoFe or Fe tends to form a body centered cubic (bcc) crystal orientation that prevents formation of the fcc structure for a CoFe/MgO/CoFe stack. A popular solution to this problem is to deposit amorphous CoFeB or FeB rather than CoFe or Fe. As a result, there is no template for crystal structure growth until annealing when B tends to diffuse away from the tunnel barrier to leave a CoFe or Fe interface with the metal oxide tunnel barrier. Meanwhile, MgO forms a fcc structure that induces fcc crystal growth in the adjoining magnetic layers. The boron content in the CoFeB and FeB layers is about 20% or less since B needs to diffuse away from the interfaces with the tunnel barrier layer to achieve high TMR ratio.
In order to realize a smaller Hc but still maintain a high TMR ratio, the industry tends to use CoFeB as the free layer in a TMR sensor. Unfortunately, the magnetostriction (λ) of a CoFeB free layer is considerably greater than the maximum acceptable value of about 5×10−6 for high density memory applications. Furthermore, a free layer may include a non-magnetic insertion layer (INS) in a FL1/INS/FL2 stack, for example, where the insertion layer is sandwiched between two ferromagnetic layers (FL1, FL2) to provide anti-ferromagnetic coupling or a moment diluting effect. However, the non-magnetic materials do not bind well with CoFeB and tend to diffuse at elevated temperatures along grain boundaries in crystalline magnetic layers. As a result, non-magnetic metals may diffuse through a free layer or reference layer into the tunnel barrier during or after annealing, and disrupt the insulation property of the barrier thereby causing a device defect. This type of diffusion is even more pronounced in semiconductor devices wherein MRAM devices are integrated (embedded) with complementary metal-oxide-semiconductor (CMOS) units that are processed at temperatures as high as 400° C. Thus, an improved free layer (or reference layer) design is needed to reduce non-magnetic metal diffusion into a tunnel barrier layer while maintaining other MTJ properties such as low λ, Hc, and Hin, and high TMR ratio following process temperatures as high as 400° C.